1. Field of the Invention
The present invention generally elates to semiconductor memories, and more particularly to a semiconductor memory in which a voltage raising circuit is capable of compensating a raised voltage for its variations caused by a source voltage and temperature.
2. Description of the Related Art
FIG. 1 shows a conventional flash memory. As shown in this diagram, the flash memory comprises a cell array 101, a reference cell 102, a sense amplifier 103, a control circuit 104, a voltage raising circuit 105, switches 102 through 123, and MOS (metal oxide semiconductor) transistors 124 through 126.
Also, the cell array 101 consists of a plurality of memory cells 110 through 113 for storing data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
By way of example, a description is given below with respect to how the data is read out of the memory cell 110 of the cell array 101 of the flash memory.
The control circuit 104 sends a voltage raising signal KICKB to the voltage raising circuit 105. When the voltage raising circuit 105 receives the KICKB signal, it raises and outputs a voltage to a node xe2x80x9caxe2x80x9d.
Also, in order to select a word line WL0, the control circuit 104 outputs a word-line selecting signal WSEL0 to turn on the switch 120. Thus, the voltage raised by the voltage raising circuit is applied to the word line WL0.
Also, in order to select a bit line B0, the control circuit 104 outputs a bit-line selecting signal BSEL0 to turn on the MOS transistor 124.
Also, in order to select a reference cell, the control circuit 104 simultaneously outputs two selecting signals WSEL and BSEL to turn on the switch 123 and the MOS transistor 126, respectively. Thus, an electric current flowing through the memory cell 110 and an electric current flowing through the reference cell 102 are inputted into the sense amplifier 103, where the two electric currents are compared.
If the electric current flowing through the memory cell 110 is larger than the electric current flowing through the reference cell 102, then xe2x80x9c1xe2x80x9d is outputted from an output D of the sense amplifier 103, whereas if smaller, then xe2x80x9c0xe2x80x9d is outputted from the output D thereof. The date xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is thus read out of the memory cell 110.
Similarly, the date xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d can be read out of the other memory cells 111, 112 and 113 as the previously described.
FIG. 2 is a graph showing various relationships between gate voltages Vg and drain currents Id with respect to the memory cells 110 through 113 of the cell array 101 and the reference cell 102.
As can be seen from FIG. 2, a solid line 201 shows a relationship between the gate voltages Vg and the drain currents Id in a case where xe2x80x9c1xe2x80x9d is stored in the memory cells 110 through 113 of the cell array 101. A solid line 202 shows a relationship between the gate voltages Vg and the drain currents Id in a case where xe2x80x9c1xe2x80x9d is stored in the memory cells 110 through 113 of the cell array 101. A solid line 203 shows a relationship between the gate voltage Vg and the drain current Id of the reference cell 102.
Also, a broken line 204 shows a case where a source voltage VCC is applied to gates of the memory cells 110 through 113 of the cell array 101 and the reference cell 102. In this case, if the data xe2x80x9c1xe2x80x9d is stored in the memory cells 110 through 113 of the cell array 101, then the stored data xe2x80x9c1xe2x80x9d can be identified by the sense amplifier 103 because a drain current of the memory cells 110 through 113 is larger than that of the reference cell 102, whereas if the data xe2x80x9c0xe2x80x9d is stored therein, then the data xe2x80x9c0xe2x80x9d cannot be identified by the sense amplifier 103 because both of the drain currents are too small.
For this reason, in the case of reading the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d out of the memory cells 110 through 113, the voltage applied to the gates of memory cells 110 through 113 and the reference 102 should be raised to a voltage shown by a broken line 205.
Further, when the raised voltage 205 is lowered to a voltage shown by a broken line 206 due to variations of the source voltage VCC and temperature, as previously described, the data xe2x80x9c0xe2x80x9d cannot be read out of the memory cells 110 through 113 of the cell array 101. On the other hand, when the voltage 205 is raised to a voltage shown by a broken line 207 due to variations of the source voltage VCC and temperature, the data xe2x80x9c0xe2x80x9d may be written into the memory cells 110 through 113 of the cell array 101 .
FIG. 3 shows a conventional voltage raising circuit 105.
As shown in this diagram, the conventional voltage raising circuit 105 comprises a PMOS transistor tr1, nMOS transistors tr2, tr3 and tr15, inverters 301 through 303, capacitors Ca and Cb, and a clamp circuit 310.
The clamp circuit 310 consists of a pMOS transistor tr4, nMOS transistors tr5 and tr6, and inverters 304 and 305.
Also, FIG. 4 shows operation timing of the conventional voltage raising circuit 105.
Referring to FIGS. 3 and 4, when the KICKB signal is changed from a high level to a low level, the pMOS transistor tr1 turns ON and a level of the KICK0 signal become high. At the same time, the nMOS transistor tr3 and the nMOS transistor tr15 turn OFF and the node bb4 becomes floating. A voltage applied to the node bb4 is raised higher than the source voltage VCC due to coupling by capacitance between a drain and a gate of the nMOS transistor tr2, and thereby the nMOS transistor tr2 turns ON so as to charge the capacitors Ca and Cb rapidly.
While the KICK0 is at the high level, on the other hand, the pMOS transistor 4 and the nMOS transistors tr5 and tr6 turn ON after two stage delay of inverter 304 and the inverter 305. Thereby, the clamp circuit 310 is actuated to apply a predetermined voltage thereof to the node bb4 and control an electric current flowing through the nMOS transistor tr2. Thus, a voltage applied to the node bb3 is controlled to a voltage that is just Vth, a threshold value of the nMOS transistor tr2, lower than the voltage applied to the node bb4. That is, the voltage applied to the node bb3 is (bb4xe2x88x92Vth) as shown in FIG. 4.
A raised voltage Va applied to the node xe2x80x9caxe2x80x9d can be obtained by taking the form
Va=VCC+[Ca/(Ca+Cb)]xc3x97bb3
where VCC denotes the source voltage, Ca denotes capacitance for raising a voltage, Cb denotes parasitical capacitance of the node xe2x80x9caxe2x80x9d, and bb3 denotes the voltage applied to the node bb3.
When the KICKB is changed from the low level to the high level, the node bb3 becomes a ground level.
It should be noted that it takes several nano-seconds to raise the voltage applied to the node bb3 to the predetermined voltage while the KICKB signal is kept at the low level, and thereafter it takes several tens of nano-seconds to make the KICKB signal be high again.
Table 1 shows a dependency of the conventional voltage raising circuit of FIG. 3 on the source voltage VCC.
As can be understood from the Table 1, when the source voltage VCC is raised from 2.6 V to 3.7 V, the voltage Va applied to the node xe2x80x9caxe2x80x9d is raised by 1.32 V from 4.11 V to 5.43 V. Accordingly, the voltage Va applied to the node xe2x80x9caxe2x80x9d has the positive dependency on the source voltage VCC.
Further, Table 2 shows a dependency of the conventional voltage raising circuit of FIG. 3 on the temperature.
As can be understood from the Table 2, when the temperature is raised from xe2x88x9255xc2x0 C. to 140xc2x0 C., the voltage Va applied to the node xe2x80x9caxe2x80x9d is lowered by 0.17 V from 4.65 V to 4.48 V. This is because the higher the temperature is, the slower it is that the voltage applied to the node bb3 is controlled to a voltage determined by the clamp circuit 310 in a given time. Accordingly, the voltage Va applied to the node xe2x80x9caxe2x80x9d has the negative dependency on the temperature.
Thus, the higher the source voltage VCC and the lower the temperature become, the higher voltage Va applied to the node xe2x80x9caxe2x80x9d becomes, to the contrary the lower the source voltage VCC and the higher the temperature become, the lower voltage Va applied to the node xe2x80x9caxe2x80x9d becomes.
As a result, the conventional voltage raising circuit of FIG. 3 brings about such a problem that in the case where the source voltage VCC is low and the temperature is high, the data xe2x80x9c0xe2x80x9d may not be read out of the memory cells 110 through 113 of the cell array 101, whereas in the case where the source voltage VCC is high and the temperature is low, the data xe2x80x9c0xe2x80x9d may be written into the memory cells 110 through 113 of the cell array 101.
It is a general object of the present invention to provide a voltage raising circuit of a semiconductor memory, in which the above problem can be eliminated.
Another and a more specific object of the present invention is to provide a voltage raising circuit of a semiconductor memory, said voltage raising circuit comprising:
a compensating circuit having a negative dependency on a source voltage for controlling a variation of a raised voltage, said variation being caused by a variation of said source voltage.
Still another object of the present invention is to provide a voltage raising circuit of a semiconductor memory, said voltage raising circuit comprising:
a compensating circuit having a positive dependency on temperature for controlling a variation of a raised voltage, said variation being caused by a variation of said temperature.
Still another object of the present invention is to provide a voltage raising circuit of a semiconductor memory, said voltage raising circuit comprising:
a compensating circuit having:
a negative dependency on a source voltage for controlling a first variation of a raised voltage, said first variation being caused by a variation of said source voltage; and
a positive dependency on temperature for controlling a second variation of said raised voltage, said second variation being caused by a variation of said temperature.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.